Figure 9, Cs8406 – Cirrus Logic CS8406 User Manual

Page 15

background image

DS580F6

15

CS8406

U[0]

U[2]

Data [4]

Data [5]

Data [6]

Data [7]

Data [8]

Data [0]*

Data [2]*

Data [4]*

Z

Y

X

* Assume MMTLR = 0

Data [1]*

Data [3]*

Data [5]*

Z

Y

X

* Assume MMTLR = 1

Tth

VLRCK

U

SDIN

TXP(N)

TCBL

TXP(N)

Figure 9. AES3 Transmitter Timing for C, U, and V Pin Input Data, Mono Mode

Note:

1. T

setup



15% AES3 frame rate

2. T

hold

= 0

3. T

th

> 3 OMCKS if TCBL is an input