1 interrupt enable registers, 2 interrupt status registers – Cirrus Logic CS61880 User Manual
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CS61880
DS450PP3
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14.33.1 Interrupt Enable Registers
The Interrupt Enable registers:
(See Section 14.7 on page 36),
DFM Interrupt Enable Register (07h)
(See Section 14.21 on page 39)
,
enable
changes in status register state to cause an interrupt
on the INT pin. Interrupts are maskable on a per
channel basis. When an Interrupt Enable register
bit is 0, the corresponding Status register bit is dis-
abled from causing an interrupt on the INT pin.
NOTE: Disabling an interrupt has no effect on the sta-
tus reflected in the associated status register.
14.33.2 Interrupt Status Registers
The following interrupt status registers:
(See Section 14.10 on page 36),
,
indicate a change in status of the corre-
sponding status registers in host mode. Reading
these registers clears the interrupt, which deacti-
vates the INT pin.