Cirrus Logic CS61880 - Manual (Page 16)

CS61880
16 DS450PP3
3.6 Digital Rx/Tx Data I/O
SYMBOL LQFP FBGA TYPE DESCRIPTION
TCLK0 36 N1 I
Transmit Clock Input Port 0
- When TCLK is active, the TPOS and TNEG pins function
as NRZ inputs that are sampled on the falling edge of
TCLK.
- If MCLK is active, TAOS will be generated when TCLK is
held High for 16 MCLK cycles.
NOTE: MCLK is used as the timing reference during TAOS
and must have the appropriate stability.
- If TCLK is held High in the absence of MCLK, the TPOS
and TNEG inputs function as RZ inputs. In this mode, the
transmit pulse width is set by the pulse-width of the signal
input on TPOS and TNEG. To enter this mode, TCLK must
be held high for at least 12
µ
s.
- If TCLK is held Low, the output drivers enter a low-power,
high impedance state.
TPOS0/TDATA0
TNEG0/UBS
37
38
N2
N3
I
I
Transmit Positive Pulse/Transmit Data Input Port 0
Transmit Negative Pulse/Unipolar-Bipolar Select Port 0
The function of the TPOS/TDATA and TNEG/UBS inputs
are determined by whether Unipolar, Bipolar or RZ input
mode has been selected.
Bipolar Mode - In this mode, NRZ data on TPOS and
TNEG are sampled on the falling edge of TCLK and trans-
mitted onto the line at TTIP and TRING respectively. A
“High” input on TPOS results in transmission of a positive
pulse; a “High” input on TNEG results in a transmission of a
negative pulse. The translation of TPOS/TNEG inputs to
TTIP/TRING outputs is as follows:
Unipolar mode - Unipolar mode is activated by holding
TNEG/UBS “High” for more than 16 TCLK cycles, when
MCLK is present. The falling edge of TCLK samples a uni-
polar data steam on TPOS/TDATA.
RZ Mode - To activate RZ mode tie TCLK “High” in the
absence of MCLK. In this mode, the duty cycle of the
TPOS and TNEG inputs determine the pulse width of the
output signal on TTIP and TRING.
Table 5. Bipolar Mode Translations
TPOS TNEG OUTPUT
0 0 Space
1 0 Positive Mark
0 1 Negative Mark
1 1 Space