Cirrus Logic CS61880 - Manual (Page 39)

CS61880
DS450PP3 39
14.21 AIS Interrupt Enable Register (14h)
14.22 AIS Interrupt Status Register (15h)
14.23 AWG Broadcast Register (16h)
14.24 AWG Phase Address Register (17h)
14.25 AWG Phase Data Register (18h)
BIT NAME Description
[7:0] AISE 7-0 This register enables changes in the AIS Status register to be reflected in the AIS Interrupt
Status register, thus causing an interrupt on the INT pin. Register bits default to 00h after
power-up or reset.
BIT NAME Description
[7:0] AISI 7-0
Bit n is set to “1” to indicate a change of status of bit n in the AIS Status Register. The bits in
this register indicate which channel changed in status since the last cleared AIS interrupt.
Register bits default to 00h after power-up or reset.
BIT NAME Description
[7:0] AWGB 7-0
Setting bit n to “1” causes the phase data in the AWG Phase Data Register to be written to
the corresponding channel or channels simultaneously. (Refer to
Arbitrary Waveform Gen-
erator (See Section 15 on page 42). Register bits default to 00h after power-up or reset.
BIT NAME Description
[7:5] AWGA These bits specify the target channel 0-7. (Refer to Arbitrary Waveform Generator (See
Section 15 on page 42). Register bits default to 00h after power-up or reset.
[4:0] PA[4:0] These bits specify 1 of 24 phase sample address locations of the AWG, that the phase data
in the AWG Phase Data Register is written to or read from. Register bits default to 00h
after power-up or reset.
BIT NAME Description
[7] RSVD RESERVED (This bit must be set to 0.)
[6:0] AWGD [6:0]
These bits are used for the pulse shape data that will be written to or read from the AWG
phase location specified by the AWG Phase Address Register. The value written to or read
from this register will be written to or read from the AWG phase sample location specified by
the AWG Phase Address register. A software reset through the Software Reset Register
does not effect the contents of this register. The data in each phase is a 7-bit 2’s complement
number (the maximum positive value is 3Fh and the maximum negative value is 40h). (Refer
to
Arbitrary Waveform Generator (See Section 15 on page 42). Register bits default to
00h after power-up.