Cirrus Logic CDB53L30 - Manual (Page 5)

5 DS963DB1
CDB53L30
1.7 Synchronization I/O
The Serial Audio I/O header J29 provides a MCLK input pin and MCLK output pin. The MCLK IN pin can be used to provide
an externally generated MCLK to the board. The MCLK OUT pin provides either a buffered version of the onboard
generated MCLK or a buffered version of the MCLK IN signal. By providing a buffered version of the MCLK IN signal, the
MCLK OUT pin may be used for daisy chaining an additional CDB53L30. This is useful when the external clock source
does not have sufficient output drive capability to support multiple parallel loads. To enable the various MCLK routing
options, use the MCLK buffer control drop-down boxes in the “Board Config” tab in the FlexGUI.
1.7 Synchronization I/O
For applications requiring more than two CS53L30 devices, two CDB53L30 boards may be linked using the Sync I/O
header J33. This will allow up to four CS53L30 devices to be synchronized using the multichip synchronization protocol.
The direction of the sync signal is configured using jumper pin block J37. For more information on enabling the
synchronization protocol, see the CS53L30 data sheet.
1.8 Control Port Interface
The Cirrus Logic FlexGUI software application (downloadable from http://www.cirrus.com/msasoftware ) provides users an
easy and intuitive way to configure the CDB53L30. A Windows ® -compatible PC with USB connectivity is required to run
FlexGUI.
The CDB53L30’s onboard microcontroller handles the USB communication with FlexGUI and the I 2 C control port interface
of the CS53L30. The control port interface and the control I/O signals (INT, RST, and MUTE) are routed through jumper
pin block J4. When the pin columns marked “FlexGUI CNTL” are shunted, the microcontroller handles all communication
between the FlexGUI application and the CS53L30. To interface to an external system, the shunts on J4 should be
removed and the external signals should be connected to the pin columns marked “EXT SYS” (note the GND pins on the
right hand side of the header).
The INT, RST, and MUTE control signals for the two CS53L30 devices may be ganged together using the “CONTROL
SHORTS” jumper pin block J34. This allows both devices to share a single set of control signals. To enable ganging of a
control, apply a shunt to the desired signal on J34. When ganging a control, remove one of the associated FlexGUI control
jumpers from J4 to prevent contention between the two ganged control signals from the microcontroller.
1.9 Layout Reference
The CDB53L30 utilizes a six-layer PCB that allows for optimal trace and power routing to the CS53L30 devices and
surrounding circuitry. Local decoupling capacitors for the CS53L30 are placed as close as possible to the device. The
CDB53L30 uses a topside-only component placement without compromise to placement of critical components, but a
double-sided placement is also be feasible. Ground fill is used extensively on the component layer to isolate critical nets
where possible.