Cirrus Logic CDB53L30 - Manual (Page 18)

18 DS963DB1
CDB53L30
5 Performance Plots
Figure 5-5. Output FFT, Preamp Setting: +20 dB,
PGA Setting: 0 dB, 1 kHz, –1 dBFS
Figure 5-6. Output FFT, Preamp Setting: +20 dB,
PGA Setting: +12 dB, 1 kHz, –1 dBFS
Figure 5-7. Output FFT, 1 kHz, –60 dBFS Figure 5-8. Output FFT, No Input
Figure 5-9. Frequency Response, Notch Filter Disabled,
Preamp Bypassed (0 dB), –1 dBFS
Figure 5-10. Frequency Response, Notch Filter Enabled,
Preamp Bypassed (0 dB), –1 dBFS
G
%
)
6
N N N N N
+]
G
%
)
6
N N N N N
+]
G
%
)
6
N N N N N
+]
G
%
)
6
N N N N N
+]
G
%
)
6
N N N N N
+]
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
Note: The low-frequency roll-off
is due to the corner frequency set
by the DC blocking cap (0.1
F)
and the input impedance (50 k
 
when the preamp setting is 0 dB).
G
%
)
6
N N N N N
+]
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7
Note: The low-frequency roll-off
is due to the corner frequency set
by the DC blocking cap (0.1
F)
and the input impedance (50 k  
when the preamp setting is 0 dB).