Cirrus Logic CDB53L30 - Manual (Page 24)

24 DS963DB1
CDB53L30
6 Schematics
Figure 6-3. Master Clock PLL and Routing Buffers
Master Clock PLL
I2C Address: 0x9C
Optional LRCK reference
To MCLK routing buffers
(from Serial Audio Header)
C127
COG
1000pF
R200 22.1
1 VD
2 GND
3
CLK_OUT 4
AUX_OUT 5
CLK_IN
10 SDA/CDIN
9 SCL/CCLK
8 AD0/CS
7
FILTN 6
FILTP
U15
CS2300CP-CZZ
C133
0.1uF
X5R
C134
1uF
X5R
6.3V
C135
0.1uF
X5R
R104 0
R136 0
R70 22.1
R255 0
R14 22.1
1
TRI-S
2
GND
3
OUT 4
VDD
Y1
24.576MHZ
PLL_AUX_OUT
R74 22.1
R138 NO POP
0402
R142
0
R143
0
NO POP
L1
600OHM@100MHZ
C85
1uF
X5R
6.3V
+3.3V
+3.3V
PLL.CLK_OUT2 [3] UC.I2C.SDA [4,5]
UC.I2C.SCL [4,5]
PLL.CLK_OUT1 [3]
PLL.LRCK_IN [4]
+3.3V
All buffer inputs are 5.5V tolerant,
independent of supply voltage.
Master Clock Routing
To Serial Header
From Serial Header
C49
0.1uF
X5R
R18 0
R20 0
R57 0
R58 0
C51
0.1uF
X5R
R66 0
R71 0
R72 0
R73
0
R127
10K
R128
10K
R129
10K
R130
10K
R67 0
NO POP
R26 0
NO POP
R65 22.1
R99 22.1
R97 22.1
R167 22.1 2 A1
1 OE
5 A2
7 OE
6 Y1
3 Y2
8 VCC
4 GND
U28
NC7WZ241K8X
2 A1
1 OE
5 A2
7
OE
6 Y1
3 Y2
8
VCC 4
GND
U4
NC7WZ241K8X
+1.8V
HDR_MCLK_IN_EN [5]
VA
PLL_MCLK_EN [5]
CS53L30-1.MCLK [2]
PLL.CLK_OUT1 [3]
+1.8V
VA
PLL.CLK_OUT2 [3]
PLL_MCLK_OUT_EN [5]
HDR_MCLK_OUT_EN [5]
MCLK_OUT [4]
MCLK_IN [4]
CS53L30-2.MCLK [2]
CS8406.OMCK [4]