Cirrus Logic CS5378 - Manual (Page 32)

CS5378
DS639F3 32
9.3.2 SPI registers
The SPI registers are shown in Figure 19 and are
24-bit registers mapped into an 8-bit register space
as high, mid, and low bytes. See “SPI Registers” on
page 66 for the bit definitions of the SPI registers.
9.3.3 Serial transactions
A serial transaction to the SPI registers starts with
an SPI opcode, followed by an address, and then
some number of data bytes written or read starting
at that address.
Typical serial write transactions require sending
groups of 5, 8, or 11 total bytes to the SPICMD or
SPIDAT1 registers:
5-byte write to SPICMD
02 03 12 34 56
5-byte write to SPIDAT1
02 06 12 34 56
8-byte write to SPICMD, SPIDAT1
02 03 12 34 56 AB CD EF
8-byte write to SPIDAT1, SPIDAT2
02 06 12 34 56 AB CD EF
11-byte write to SPICMD, SPIDAT1, SPIDAT2
02 03 12 34 56 AB CD EF 65 43 21
Typical serial read transactions require groups of 3
or 5 bytes, split between writing into MOSI and
reading from MISO.
3-byte read of mid-byte of SPICTRL
MOSI: 03 01 00
MISO: xx xx 12
5-byte read of SPIDAT1
MOSI: 03 06 00 00 00
MISO: xx xx 12 34 56
9.3.4 Multiple serial transactions
Some configuration commands require multiple se-
rial transactions to complete. There must be a
small delay between transactions for the CS5378 to
process the incoming data. Two methods can be
used to ensure the CS5378 is ready to receive the
next configuration command.
1) Delay a fixed 1 ms period to guarantee enough
time for the command to be completed.
2) Verify the status of the E2DREQ bit by reading
the SPICTRL register. When low, the CS5378 is
ready for the next command.
9.3.5 Polling E2DREQ
One transaction type that can always be performed
no matter the delay from the previous configuration
command is reading E2DREQ in the mid-byte of
the SPICTRL register. A 3-byte read transaction.
MOSI: 03 01 00
MISO: xx xx 01 <- E2DREQ bit high
MISO: xx xx 00 <- E2DREQ bit low
The E2DREQ bit reads high while a serial transac-
tion is being processed. When low, the digital filter
is ready to receive a new serial transaction.
Name Addr. Type # Bits Description
SPICTRL 00 - 02 R/W 8, 8, 8 SPI Control
SPICMD 03 - 05 R/W 8, 8, 8 SPI Command
SPIDAT1 06 - 08 R/W 8, 8, 8 SPI Data 1
SPIDAT2 09 - 0B R/W 8, 8, 8 SPI Data 2
Figure 19. SPI Registers