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Figure 1. master mode serial audio port timing, Figure 2. slave mode serial audio port timing, Figure 3. format 0, 24-bit data left-justified – Cirrus Logic CS5346 User Manual

Page 15: Figure 4. format 1, 24-bit data i·s, Figure 1.master mode serial audio port timing, Figure 2.slave mode serial audio port timing, Figure 3.format 0, 24-bit data left-justified, Figure 4.format 1, 24-bit data i²s, Figure 1, Cs5346

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DS861PP3

15

CS5346

slr

t

SDOUT

SCLK

Output

LRCK

Output

sdo

t

slr

t

SDOUT

SCLK

Input

LRCK

Input

sdo

t

sclkh

t

sclkl

t

sclkw

t

Figure 1. Master Mode Serial Audio Port Timing

Figure 2. Slave Mode Serial Audio Port Timing

Figure 3. Format 0, 24-Bit Data Left-Justified

LRCK

SCLK

SDATA

+3 +2 +1

+5 +4

-1 -2 -3 -4 -5

+3 +2 +1

+5 +4

MSB

-1 -2 -3 -4

Channel A - Left

Channel B - Right

LSB

LSB

MSB

Figure 4. Format 1, 24-Bit Data I²S

LRCK

SCLK

SDATA

+3 +2 +1

+5 +4

MSB

-1 -2 -3 -4 -5

+3 +2 +1

+5 +4

-1 -2 -3 -4

Channel A - Left

Channel B - Right

LSB

MSB

LSB

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