Cirrus Logic CS5346 - Manual

Copyright
 Cirrus Logic, Inc. 2012
(All Rights Reserved)
Preliminary Product Information
This document contains information for a product under development.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux
ADC Features

Multi-bit Delta–Sigma Modulator
 103 dB Dynamic Range
 -95 dB THD+N

Stereo 6:1 Input Multiplexer
 Programmable Gain Amplifier (PGA)
– ± 12 dB Gain, 0.5-dB Step Size
– Zero-crossing, Click-free Transitions
 Stereo Microphone Inputs
– +32 dB Gain Stage
– Low-noise Bias Supply
 Up to 192 kHz Sampling Rates
 Selectable 24-bit, Left-justified or I²S Serial
Audio Interface Formats
System Features
 Power-down Mode
 +5 V Analog Power Supply, Nominal
 +3.3 V Digital Power Supply, Nominal
 Direct Interface with 3.3 V to 5 V Logic Levels
 Pin Compatible with CS5345 (*See Section 2
for details.)
General Description
The CS5346 integrates an analog multiplexer, program-
mable gain amplifier, and stereo audio analog-to-digital
converter. The CS5346 performs stereo analog-to-digi-
tal (A/D) conve rsion of 24-bit serial values at sa mple
rates up to 192 kHz.
A 6:1 stereo input multiplexer is included for selecting
between line-level and microphone-level inputs. The
microphone input path includes a +32 dB gain stage
and a low-noise bias voltage supply. The PGA is avail-
able for line or microphone inputs and provides
gain/attenuation of ±12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5th-
order, multi-bit delta-sigma modulator and digital filter-
ing/decimation. Sampled data is transmitted by the
serial audio interface at rates from 8 kHz to 192 kHz in
either Slave or Master Mode.
Integrated level translators allow easy interfacing be-
tween the CS5346 and other devices operating over a
wide range of logic levels.
The CS5346 is available in a 48-pin LQFP package in
Commercial (-40° to +85° C) grade. The CDB5346 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. Please re-
fer to “Ordering Information” on page 38 for complete
details.
3.3 V to 5 V
Low-Latency
Anti-Alias Filter
Internal Voltage
Reference
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
Low-Latency
Anti-Alias Filter
High Pass
Filter
High Pass
Filter
Stereo Input 1
Serial
Audio
Output
3.3 V 5 V
MUX
PC
M
S
eri
al
In
te
rface
Register Configuration
Le
vel
Tran
slat
or
Stereo Input 2
Stereo Input 3
Stereo Input 4 /
Mic Input 1 & 2
Stereo Input 5
Stereo Input 6
PGA
+32 dB
+32 dB
Le
vel
T
ra
nslat
or
Reset
I²C  /SPI 
Control Data
Interrupt
Overflow
Left PGA Output
Right PGA Output
PGAA
AUG ‘12
DS861PP3
CS5346