Ac ’97 serial port timing, Cs4205 – Cirrus Logic CS4205 User Manual
Page 10
CS4205
10
DS489PP4
AC ’97 SERIAL PORT TIMING
Standard test conditions unless otherwise noted: T
ambient
= 25° C,
AVdd = 5.0 V, DVdd = 3.3 V; C
L
= 55 pF load.
Parameter
Symbol
Min
Typ
Max
Unit
RESET Timing
RESET# active low pulse width
T
rst_low
1.0
-
-
µs
RESET# inactive to BIT_CLK start-up delay
(XTL mode)
(OSC mode)
(PLL mode)
T
rst2clk
-
-
-
4.0
4.0
2.5
-
-
-
µs
µs
ms
1st SYNC active to CODEC READY ‘set’
T
sync2crd
-
62.5
-
µs
Vdd stable to RESET# inactive
T
vdd2rst#
100
-
-
µs
Clocks
BIT_CLK frequency
F
clk
-
12.288
-
MHz
BIT_CLK period
T
clk_period
-
81.4
-
ns
BIT_CLK output jitter (depends on XTL_IN source)
-
-
750
ps
BIT_CLK high pulse width
T
clk_high
36
40.7
45
ns
BIT_CLK low pulse width
T
clk_low
36
40.7
45
ns
SYNC frequency
F
sync
-
48
-
kHz
SYNC period
T
sync_period
-
20.8
-
µs
SYNC high pulse width
T
sync_high
-
1.3
-
µs
SYNC low pulse width
T
sync_low
-
19.5
-
µs
Data Setup and Hold
Output propagation delay from rising edge of BIT_CLK
T
co
8
10
12
ns
Input setup time from falling edge of BIT_CLK
T
isetup
10
-
-
ns
Input hold time from falling edge of BIT_CLK
T
ihold
0
-
-
ns
Input signal rise time
T
irise
2
-
6
ns
Input signal fall time
T
ifall
2
-
6
ns
Output signal rise time
(Note 4)
T
orise
2
4
6
ns
Output signal fall time
(Note 4)
T
ofall
2
4
6
ns
Misc. Timing Parameters
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
T
s2_pdown
-
0.2
1.0
µs
SYNC pulse width (PR4) Warm Reset
T
sync_pr4
1.0
-
-
µs
SYNC inactive (PR4) to BIT_CLK start-up delay
T
sync2clk
162.8
285
-
ns
Setup to trailing edge of RESET# (ATE test mode) (Note 4)
T
setup2rst
15
-
-
ns
Rising edge of RESET# to Hi-Z delay
(Note 4)
T
off
-
-
25
ns