PNI Legacy Comm Board - Manual (Page 29)

PNI Corporation 133 Aviation Blvd., Suite 101, Santa Rosa, CA 95403-1084 USA;, Fax: (707) 566-2261
For the most current specifications, please visit our website at:
www.pnicorp.com
Page 29 of 42
SPI INTERFACE TO SENSOR MODULE
Table 14: SPI Pin Descriptions
Pin Name Description
1 SCLK Serial clock output for the SPI port
2 MISO Serial data input. Master In Slave Out
3 MOSI Serial data output. Master Out Slave In
4 SSNOT Active low chip select for SPI port
5 DRDY Data ready input (not supported by V2Xe module)
6 SYNC Sync output
7 GND Ground
8 GIO0 Reserved I/O
9 GIO1 Reserved I/O
10 GIO2 Reserved I/O
11 GIO3 Reserved I/O
12 VDD Supply voltage, 3 VDC regulated
13 VCC Unregulated CommBoard input supply voltage
14 GND Ground
SPI Port Pin Descriptions
MOSI – Master Out Slave In
The data sent from the CommBoard. Data is transferred most significant bit first. The MOSI line will
accept data once the SPI is enabled by taking SSNOT low. Valid data must be presented at least 100 nS
before the rising edge of the clock, and remain valid for 100 nS after the edge. New data may be presented
to the MOSI pin on the falling edge of SCLK.
SSNOT - Slave Select Line
Selects the module as the operating slave device. The SSNOT line must be low prior to data transfer and
must stay low during the entire transfer. Once the command byte is received by the module, and the module
begins to execute the command, the SSNOT line can be deselected until the next SPI transfer.
SCLK – Serial Clock
Used to synchronize both the data in and out through the MISO and MOSI lines. SCLK is generated by the
CommBoard. SCLK should be 1 MHz or less. The CommBoard is configured to run as a master device,
making it an output. One byte of data is exchanged over eight clock cycles. Data is captured by the
CommBoard on the rising edge of SCLK. Data is shifted out and presented to the module on the MOSI pin
on the falling edge of SCLK.
MISO – Master In Slave Out
The data sent from the module to the CommBoard. Data is transferred most significant bit first. The MISO
line is placed in a high impedance state if the slave is not selected (SSNOT = 1).
CommBoard
SPI Interface to Sensor Module