Clear-Com ICS-2003 - Manual (Page 45)

Clear-Com Communication Systems
ICS-2003 Intercom Panel Instruction Manual
3 - 5
TECHNICAL REFERENCE
Figure 3-9: Digital Block Diagram—ICS-2003 Main PCB
ICS-2003 DIGIT
AL
BLOCK DIAGRAM
Jan. 14, 1998
PROGRAM MEMOR
Y
LO BYTE
PROGRAM MEMOR
Y
HI BYTE
RAM MEMOR
Y
LO BYTE
RAM MEMOR
Y
HI BYTE
DISPLA
Y CONTROLLER
DISPLA
Y
MEMOR
Y
LO BYTE
DISPLA
Y
MEMOR
Y
HI BYTE
ADDRESS BUS
A1-A19
DA
T A BUS D0-D15
128K X 8
128K X 8
128K X 8
128K X 8
32K X 8
32K X 8
CE0 CE1
ADDRESS DECODE
CE2
DISPLA
Y
COM MODULE
CE3
CONTROL
BUS
RXD1 TXD1
CLOCK OSC
RESET
MICRO-PROCESSOR
ACCESSOR
Y
P ANELS
PB8 PB9 PB10 PB1
1
PA
0
PA
1
SERIAL TEST POR
T
RXD2 TXD2
XPDOUT XPDIN XPDCLK XPDSTRB
PA
2
PA
3
PA
4
PA
5
PA
6
PA
7
PA
8
PA
9
P A10 P A12
SPRXD SPTXD SPCLK
PB3 PB5 PB6 PB7
TIN1
T OUT2 TEST
FRNTPNL
AUDIOLEV1 AUDIOLEV2 AUDIOCNTRL
TINSEL0 TINSEL1
ADAC & D ATA SELECT
FRONT P ANEL POTS
TIN1
TINSEL0 TINSEL1
SPRXD SPTXD SPCLK
FRNTPNL
FRONT
P
ANEL
SWITCHES AND LEDS
DIGIT
ALL
Y
CONTROLLED POTS
SPTXD SPCLK
AUDIOLEV2
DIGIT
ALL
Y
CONTROLLED POTS
SPCLK SPTXD
AUDIOLEV1
ANNOUNCE T ONE FIL
TER
ANNOUNCE T ONE OUTPUT
T
O
AUDIO
AP
TEST
POR
T
SPRXD SPTXD SPCLK TEST
SPI SERIAL
DA
T A BUS
ADAC CONTROL
DTMF GENERA
T O
R
SPI 8 BIT SHIFT OUT
REG
SPI 8 BIT SHIFT IN REG
MUTE RELA
Y
AUX RELA
Y
T ALK ENABLE SA
ENABLE
LOGIC IN 1 LOGIC IN 2
HEAD SENSE
SPI 8 BIT SHIFT OUT
REG
INTERNAL
IN/OUT
CONTROL
REGISTERS UNDER SPI CONTROL SPITXD
SPICLK
AUDIOCNTRL
SPICLK
AUDIOCNTRL
SPICLK
AUDIOCNTRL
SPIRXD
AUDIOLEV3
FPSTRB
DIGIT
ALL
Y
CONTROLLED POTS
SPTXD SPCLK
AUDIOLEV3
SPK
SPK
EAR 1
EAR 1
EAR 2
EAR 2
INTERCOM VOLUME
PROGRAM VOLUME
MISC. CONTROLS
P ANEL MIC HEAD MIC SIDE EAR 1 SIDE EAR 2