Attiny28l/v, Instruction set summary (continued) – Rainbow Electronics ATtiny28L User Manual
Page 70
70
ATtiny28L/V
1062E–10/01
DATA TRANSFER INSTRUCTIONS
LD
Rd, Z
Load Register Indirect
Rd
← (Z)
None
2
ST
Z, Rr
Store Register Indirect
(Z)
← Rr
None
2
MOV
Rd, Rr
Move between Registers
Rd
← Rr
None
1
LDI
Rd, K
Load Immediate
Rd
=← K
None
1
IN
Rd, P
In Port
Rd
← P
None
1
OUT
P, Rr
Out Port
P
← Rr
None
1
LPM
Load Program Memory
R0
←=(Z)
None
3
BIT AND BIT-TEST INSTRUCTIONS
SBI
P, b
Set Bit in I/O Register
I/O(P,b)
← 1
None
2
CBI
P, b
Clear Bit in I/O Register
I/O(P,b)
← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1)
← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n)
← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left through Carry
Rd(0)
← C, Rd(n+1) ← Rd(n), C ← Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right through Carry
Rd(7)
← C, Rd(n) ← Rd(n+1), C ← Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n)
← Rd(n+1), n = 0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)
← Rd(7..4), Rd(7..4) ← Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s)
← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s)
← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T
← Rr(b)
T
1
BLD
Rd, b
Bit Load from T to Register
Rd(b)
← T
None
1
SEC
Set Carry
C
← 1
C
1
CLC
Clear Carry
C
← 0
C
1
SEN
Set Negative Flag
N
←=1
N
1
CLN
Clear Negative Flag
N
← 0
N
1
SEZ
Set Zero Flag
Z
← 1
Z
1
CLZ
Clear Zero Flag
Z
← 0
Z
1
SEI
Global Interrupt Enable
I
← 1
I
1
CLI
Global Interrupt Disable
I
← 0
I
1
SES
Set Signed Test Flag
S
← 1
S
1
CLS
Clear Signed Test Flag
S
← 0
S
1
SEV
Set Two’s Complement Overflow
V
=← 1
V
1
CLV
Clear Two’s Complement Overflow
V
← 0
V
1
SET
Set T in SREG
T
=← 1
T
1
CLT
Clear T in SREG
T
←=0
T
1
SEH
Set Half-carry Flag in SREG
H
← 1
H
1
CLH
Clear Half-carry Flag in SREG
H
← 0
H
1
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
Watchdog Reset
(see specific descr. for WDR/timer)
None
1
Instruction Set Summary (Continued)
Mnemonic
Operands
Description
Operation
Flags
# Clocks