Rainbow Electronics ATtiny28L - Manual (Page 21)

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ATtiny28L/V
1062E–10/01
cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configured
as level interrupt.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny28 and always reads as zero.
• Bit 4 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. TOV0 is
cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 in ICR and TOV0
are set (one), the Timer/Counter0 Overflow interrupt is executed.
• Bit 3..0 - Res: Reserved Bits
These bits are reserved bits in the ATtiny28 and always read as zero.
Note: 1. One should not try to use the SBI (Set Bit in I/O Register) instruction to clear individ-
ual flags in the Register. This will result in clearing all the flags in the register,
because the register is first read, then modified and finally written, thus writing ones
to all set flags. Using the CBI (Clear Bit in I/O Register) instruction on IFR will result in
clearing all bits apart from the specified bit.
External Interrupt The external interrupt is triggered by the INT pins. Observe that, if enabled, the interrupt
will trigger even if the INT pin is configured as an output. This feature provides a way of
generating a software interrupt. The external interrupt can be triggered by a falling or ris-
ing edge, a pin change or a low level. This is set up as indicated in the specification for
the Interrupt Control Register (ICR). When the external interrupt is enabled and is con-
figured as level-triggered, the interrupt will trigger as long as the pin is held low.
The external interrupt is set up as described in the specification for the Interrupt Control
Register (ICR).
Low-level Input Interrupt The low-level interrupt is triggered by setting any of the Port B pins low. However, if any
Port B pins are used for other special features, these pins will not trigger the interrupt.
For example, if the analog comparator is enabled, a low level on PB0 or PB1 will not
cause an interrupt. This is also the case for the special functions T0, INT0 and INT1. If
low-level interrupt is selected, the low level must be held until the completion of the cur-
rently executing instruction to generate an interrupt. When this interrupt is enabled, the
interrupt will trigger as long as any of the Port B pins are held low.
Sleep Modes To enter the sleep modes, the SE bit in MCUCS must be set (one) and a SLEEP instruc-
tion must be executed. The SM bit in the MCUCS register selects which sleep mode
(Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt
occurs while the MCU is in a sleep mode, the MCU awakes. The CPU is then halted for
four cycles. It executes the interrupt routine and resumes execution from the instruction
following SLEEP. The contents of the register file and I/O memory are unaltered. If a
reset occurs during sleep mode, the MCU wakes up and executes from the Reset
vector.
Idle Mode When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle
Mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys-
tem to continue operating. This enables the MCU to wake up from external triggered
interrupts as well as internal ones like Timer Overflow interrupt and Watchdog reset. If
wake-up from the Analog Comparator Interrupt is not required, the analog comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Sta-
tus register (ACSR). This will reduce power consumption in Idle Mode. Note that the
ACD bit is set by default.