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Analog comparator, Attiny28l/v – Rainbow Electronics ATtiny28L User Manual

Page 34

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34

ATtiny28L/V

1062E–10/01

Analog Comparator

The analog comparator compares the input values on the positive input PB0 (AIN0) and
negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) is higher
than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output
(ACO) is set (one). The comparator can trigger a separate interrupt exclusive to the ana-
log comparator. The user can select interrupt triggering on comparator output rise, fall or
toggle. A block diagram of the comparator and its surrounding logic is shown in Figure
28

.

Figure 28. Analog Comparator Block Diagram

Analog Comparator Control
and Status Register – ACSR

• Bit 7 – ACD: Analog Comparator Disable

When this bit is set (one), the power to the analog comparator is switched off. This bit
can be set at any time to turn off the analog comparator. When changing the ACD bit,
the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.
Otherwise, an interrupt can occur when the bit is changed. To use the analog compara-
tor, the user must clear this bit.

• Bit 6 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny28 and will always read as zero.

• Bit 5 – ACO: Analog Comparator Output

ACO is directly connected to the comparator output.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set (one) when a comparator output event triggers the interrupt mode defined
by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit
is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-
ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a
logical “1” to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the ana-
log comparator interrupt is activated. When cleared (zero), the interrupt is disabled.

PB0

PB1

Bit

7

6

5

4

3

2

1

0

$08

ACD

ACO

ACI

ACIE

ACIS1

ACIS0

ACSR

Read/Write

R/W

R

R

R/W

R/W

R

R/W

R/W

Initial Value

1

0

X

0

0

0

0

0