Rainbow Electronics ATtiny28L - Manual (Page 12)

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ATtiny28L/V
1062E–10/01
an interrupt has occurred, and is set by the RETI instruction to enable subsequent
interrupts.
• Bit 6 – T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source
and destination for the operated bit. A bit from a register in the register file can be copied
into T by the BST instruction, and a bit in T can be copied into a bit in a register in the
register file by the BLD instruction.
• Bit 5 – H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations. See the
Instruction Set description for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s comple-
ment overflow flag V. See the Instruction Set description for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetic. See the
Instruction Set description for detailed information.
• Bit 2 – N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
See the Instruction Set description for detailed information.
• Bit 1 – Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logical operation. See the
Instruction Set description for detailed information.
• Bit 0 – C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc-
tion Set description for detailed information.
Note that the status register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
Reset and Interrupt
Handling The ATtiny28 provides five different interrupt sources. These interrupts and the reset
vector each have a separate program vector in the program memory space. All the inter-
rupts are assigned to individual enable bits. In order to enable the interrupt, both the
individual enable bit and the I-bit in the status register (SREG) must be set to one.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 3. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.