Rainbow Electronics T5761 - Manual (Page 18)

18
T5760/T5761
4561B–RKE–10/02
Figure 23. Output of the Data Clock After a Successful Bit Check
The delay of the data clock is calculated as follows: t
Delay
= t
Delay1
+ t
Delay2
t
Delay1
is the delay between the internal signals Data_Out and Data_In. For the rising
edge, t
Delay1
depends on the capacitive load C
L
at Pin DATA and the external pull-up
resistor R
pup
. For the falling edge, t
Delay1
depends additionally on the external voltage V
X
(see Figure 24, Figure 25 and Figure 32). When the level of Data_In is equal to the level
of Data_Out, the data clock is issued after an additional delay t
Delay2
.
Note that the capacitive load at Pin DATA is limited. If the maximum tolerated capacitive
load at Pin DATA is exceeded, the data clock disappears (see chapter ’Data Interface’).
Figure 24. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA)
Figure 25. Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA)
Dem_out
Data_out (DATA)
DATA_CLK
'1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0'
Bit check ok
Data
Receiving mode,
bit check active Receiving mode,
data clock control
logic active
Start bit
V
Il = 0,35 * V S
V
Ih
= 0,65 * V S
V
X
DATA_CLK
Serial bi-directional
data line
t
Delay1
t
P_Data_Clk
Data_Out
Data_In
t
Delay2
t
Delay
V
Il
= 0,35 * V S
V
Ih
= 0,65 * V S
V
X
DATA_CLK
Serial bi-directional
data line
t
Delay1
t
P_Data_Clk
Data_Out
Data_In
t
Delay2
t
Delay