Rainbow Electronics T5761 - Manual (Page 10)

10
T5760/T5761
4561B–RKE–10/02
Figure 8. Polling Mode Flow Chart
Figure 9. Timing Diagram for Complete Successful Bit Check
Sleep mode:
All circuits for signal processing are
disabled. Only XTO and Polling logic is
enabled.
Output level on Pin IC_ACTIVE => low
I
S
= I
Soff
T
Sleep
= Sleep x X
Sleep
x 1024 x T
Clk
Start-up mode:
The signal processing circuits are
enabled. After the start-up time (T
Startup
)
all circuits are in stable
condition and ready to receive.
Output level on Pin IC_ACTIVE => high
I
S
= I
Son
T
Startup
Bit-check mode:
The incomming data stream is
analyzed. If the timing indicates a valid
transmitter signal, the receiver is set to
receiving mode. Otherwise it is set to
Sleep mode.
Output level on Pin IC_ACTIVE => high
I
S
= I
Son
T
Bit-check
Receiving mode:
The receiver is turned on permanently
and passes the data stream to the
connected microcontroller.
It can be set to Sleep mode through an
OFF command via Pin DATA or
Output level on Pin IC_ACTIVE => high
I
S
= I
Son
Bit check
OK ?
OFF command
Sleep: 5-bit word defined by Sleep0 to
Sleep4 in OPMODE register
X
Sleep
: Extension factor defined by
XSleepStd
according to Table 9
T
Clk
: Basic clock cycle defined by fXTO
and Pin MODE
T
Startup
: Is defined by the selected baud rate
range and TClk. The baud-rate range
is defined by Baud0 and Baud1 in
the OPMODE register.
NO
YES
POLLING/_ON.
T
Bit-check
: Depends on the result of the bit check
If the bit check is ok, T
Bit-check
depends on the number of bits to be
checked (N
Bit-check
) and on the
utilized data rate.
If the bit check fails, the average
time period for that check depends
on the selected baud-rate range and
on T
Clk
. The baud-rate range is
defined by Baud0 and Baud1 in the
OPMODE register.
Bit check
IC_ACTIVE
Data_out (DATA)
1/2 Bit
Start-up mode
( Number of checked Bits: 3 ) Bit check ok
1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
Receiving mode
Dem_out
Bit-check mode
T
Start-up
T
Bit-check