Rainbow Electronics T5761 - Manual (Page 16)

16
T5760/T5761
4561B–RKE–10/02
Figure 18 illustrates how to set the receiver back to polling mode via Pin POLLING/_ON.
The Pin POLLING/_ON must be held to low for the time period t
on2
. After the positive
edge on Pin POLLING/_ON and the delay t
on3
, the polling mode is active and the sleep
time T
Sleep
elapses.
This command is faster than using Pin DATA at the cost of an additional connection to
the microcontroller.
Figure 19 illustrates how to set the receiver to receiving mode via the Pin
POLLING/_ON. The Pin POLLING/_ON must be held to Low. After the delay t
on1
, the
receiver changes from sleep mode to start-up mode regardless the programmed values
for T
Sleep
and N
Bit-check
. As long as POLLING/_ON is held to Low, the values for T
Sleep
and N
Bit-check
will be ignored, but not deleted (see chapter ’Digital Noise Suppression’).
If the receiver is polled exclusively by a microcontroller, T
Sleep
must be programmed
to 31 (permanent sleep mode). In this case the receiver remains in sleep mode as long
as POLLING/_ON is held to High.
Data Clock
The Pin DATA_CLK makes a data shift clock available to sample the data stream into a
shift register. Using this data clock, a microcontroller can easily synchronize the data
stream. This clock can only be used for Manchester and Bi-phase coded signals.
Generation of the Data
Clock After a successful bit check, the receiver switches from polling mode to receiving mode
and the data stream is available at Pin DATA. In receiving mode, the data clock control
logic (Manchester/Bi-phase demodulator) is active and examines the incoming data
stream. This is done, like in the bit check, by subsequent time frame checks where the
distance between two edges is continuously compared to a programmable time window.
As illustrated in Figure 20, only two distances between two edges in Manchester and
Bi-phase coded signals are valid (T and 2T).
The limits for T are the same as used for the bit check. They can be programmed in the
LIMIT-register (Lim_min and Lim_max, see Table 10 and
Table 11).
The limits for 2T are calculated as follows:
Lower limit of 2T: Lim_min_2T = (Lim_min + Lim_max) - (Lim_max - Lim_min)/2
Upper limit of 2T: Lim_max_2T= (Lim_min + Lim_max) + (Lim_max - Lim_min)/2
(If the result for ’Lim_min_2T’ or ’Lim_max_2T’ is not an integer value, it will be round
up)
The data clock is available, after the data clock control logic has detected the
distance 2T (Start bit) and is issued with the delay t
Delay
after the edge on Pin DATA (see
Figure 20).
If the data clock control logic detects a timing or logical error (Manchester code viola-
tion), like illustrated in Figure 21 and Figure 22, it stops the output of the data clock. The
receiver remains in receiving mode and starts with the bit check. If the bit check was
successful and the start bit has been detected, the data clock control logic starts again
with the generation of the data clock (see Figure 23).
It is recommended to use the function of the data clock only in conjunction with the bit
check 3, 6 or 9. If the bit check is set to 0 or the receiver is set to receiving mode via the
Pin POLLING/_ON, the data clock is available if the data clock control logic has
detected the distance 2T (Start bit).
Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit.