Rainbow Electronics MAX17409 - Manual (Page 30)

MAX17409
1-Phase Quick-PWM GPU Controller
30 ______________________________________________________________________________________
Applications Information
Positive Offset
Some applications require a positive offset to shift the
output voltage to a different level. This might be neces-
sary to obtain a voltage not supported by the VID code,
or to allow a shift in the VID code mapping.
A positive offset is generated by raising the voltage at
the GNDS/OFSP pin using a resistor-divider from REF.
Refer to R14 and R20 in Figure 1. The voltage at the
GNDS/OFSP pin relative to the analog ground of the IC
sets the offset voltage that is added to the programmed
VID voltage:
and:
V TARGET = V DAC + V OFFSET
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching power
stage requires particular attention (Figure 8). If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Follow the MAX17409 Evaluation Kit layout and
use the following guidelines for good PCB layout:
• Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitter-
free operation.
• Connect all analog grounds to a separate solid cop-
per plane, which connects to the GND pin of the
Quick-PWM controller. This includes the V
CC
bypass capacitor, REF, GNDS bypass capacitors,
and compensation (CCV) components.
• Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCBs (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single
milliohm of excess trace resistance causes a mea-
surable efficiency penalty.
• Keep the high-current, gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
• CSP and CSN connections for current limiting and
voltage positioning must be made using Kelvin-sense
connections to guarantee the current-sense accuracy.
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
• Route high-speed switching nodes away from sen-
sitive analog areas (CCV, FB, CSP, CSN, etc.).
Layout Procedures
1) Place the power components first, with ground ter-
minals adjacent (low-side MOSFET source, C IN ,
C OUT , and D1 anode). If possible, make all these
connections on the top layer with wide, copper-
filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50mils to 100mils wide if the MOSFET is 1in
from the controller IC).
3) Group the gate-drive components (BST capacitors,
V DD bypass capacitor) together near the controller IC.
4) Make the DC-DC controller ground connections as
shown in Figure 1. This diagram can be viewed as
having four separate ground planes: input/output
ground, where all the high-power components go;
the power ground plane, where the PGND pin and
V
DD
bypass capacitor go; the master’s analog
ground plane where sensitive analog components
go, the master’s GND pin and V
CC bypass capaci-
tor go; and the slave’s analog ground plane where
the slave’s GND pin and V
CC bypass capacitor go.
The master’s GND plane must meet the PGND
plane only at a single point directly beneath the IC.
Similarly, the slave’s GND plane must meet the
PGND plane only at a single point directly beneath
the IC. The respective master and slave ground
planes should connect to the high-power output
ground with a short metal trace from PGND to the
source of the low-side MOSFET (the middle of the
star ground). This point must also be very close to
the output capacitor ground terminal.
5) Connect the output power planes (V CORE and sys-
tem ground planes) directly to the output filter
capacitor positive and negative terminals with multi-
ple vias. Place the entire DC-DC converter circuit as
close to the CPU as is practical.
V V
R
R R
V
GNDS OFFSET REF
= =
+
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⎝⎜
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⎠⎟
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