Rainbow Electronics MAX17409 - Manual (Page 29)

MAX17409
1-Phase Quick-PWM GPU Controller
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driver can supply sufficient current to support the gate
charge and the current injected into the parasitic gate-
to-drain capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems could
occur (see the
MOSFET Gate Drivers section).
MOSFET Power Dissipation
Worst-case conduction losses occur in the high-side
MOSFET (N
H ) is a function of the duty factor, with the
worst-case power dissipation occurring at the minimum
input voltage:
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
DS(ON) required to stay within package
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (R
DS(ON) ) losses. High-
side switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the switching losses in a high-side MOSFET
(N
H ) is difficult since it must allow for difficult quantify-
ing factors that influence the turn-on and turn-off times.
These factors include the internal gate resistance, gate
charge, threshold voltage, source inductance, and PCB
layout characteristics. The following switching-loss cal-
culation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably includ-
ing verification using a thermocouple mounted on N
H :
where C OSS is the N H MOSFET’s output capacitance,
Q G(SW) is the charge needed to turn on the N H MOSFET,
and I
GATE
is the peak gate-drive source/sink current
(2.2A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the C
x V
IN
2 x f SW switching-loss equation. If the high-side
MOSFET chosen for adequate R DS(ON) at low battery
voltages becomes extraordinarily hot when biased from
V
IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (N L ), the worst-case power
dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I
LOAD(MAX) , but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility, the circuit can be overde-
signed to tolerate:
where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (D
L
) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current during the dead
times. This diode is optional and can be removed if effi-
ciency is not critical.
Boost Capacitors
The boost capacitors (C BST ) must be selected large
enough to handle the gate charging requirements of
the high-side MOSFETs. However, high-current appli-
cations driving large high-side MOSFETS require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:
where N is the number of high-side MOSFETs used for
one regulator, and Q
GATE is the gate charge specified
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
(V
GS = 5V). Using the above equation, the required
boost capacitance would be:
Selecting the closest standard value, this example
requires a 0.22µF ceramic capacitor.
C
nC
mV
µF
BST
= × =
2 24
200
0 24 .
C
N Q
mV
BST
GATE =
×
200
I I
I
LOAD VALLEY MAX
INDUCTOR = +
⎛
⎝⎜ ⎞
⎠⎟
( )
∆
2
( )
( )
= +
⎛
⎝⎜ ⎞
⎠⎟
I
I LIR
VALLEY MAX
LOAD MAX
2
PD (NL Resistive) = 1-
V
V
OUT
IN MAX ( )
⎛
⎝
⎜
⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤⎤
⎦
⎥
⎥
( )
I R
LOAD DS ON
2
( )
PD (NH Switching) = V I f
Q
I
IN LOAD SW
G SW
GATE
( )
⎛
⎝⎝⎜ ⎞
⎠⎟
+
C V
OSS IN
2 2
2
f
SW
PD (NH Resistive) =
V
V
I R
OUT
IN
LOAD DS
⎛
⎝⎜ ⎞
⎠⎟
2
(O ON)