Rainbow Electronics MAX17409 - Manual (Page 24)

MAX17409
1-Phase Quick-PWM GPU Controller
24 ______________________________________________________________________________________
Shutdown
When SHDN goes low, the MAX17409 enters low-power
shutdown mode. PWRGD is pulled low immediately,
and the output voltage ramps down with a 1.56mV/µs
slew rate:
Slowly discharging the output capacitors by slewing the
output over a long period of time keeps the average
negative inductor current low (damped response),
thereby eliminating the negative output-voltage excur-
sion that occurs when the controller discharges the out-
put quickly by permanently turning on the low-side
MOSFET (underdamped response). This eliminates the
need for the Schottky diode normally connected
between the output and ground to clamp the negative
output-voltage excursion. After the controller reaches
the zero target, the MAX17409 shuts down completely—
the drivers are disabled (DL driven high, DH pulled
low)—the reference turns off, and the supply currents
drop to approximately 1µA (max).
When a fault condition—output UVLO or thermal shut-
down—activates the shutdown sequence, the protec-
tion circuitry sets the fault latch to prevent the controller
from restarting. To clear the fault latch and reactivate
the controller, toggle SHDN or cycle V
CC power below
0.5V typ.
Temperature Comparator (
VRHOT)
The MAX17409 also features an independent compara-
tor with an accurate threshold (V
HOT
) that tracks the
analog supply voltage (V
HOT
= 0.3V
CC
). This makes the
thermal trip threshold independent of the V CC supply
voltage tolerance. Use a resistor- and thermistor-divider
between V
CC and GND to generate a voltage-regulator
overtemperature monitor. Place the thermistor as close
to the MOSFETs and inductors as possible.
Fault Protection (Latched)
Output Overvoltage (OVP) Protection
The OVP circuit is designed to protect the processor
against a shorted high-side MOSFET by drawing high
current and blowing the battery fuse. The MAX17409
continuously monitors the output for an overvoltage fault.
The controller detects an OVP fault if the output voltage
exceeds the set VID DAC voltage by more than 300mV,
subject to a minimum OVP threshold of 0.8V. During
pulse-skipping operation (SKIP = high), the controller
initially sets the OVP threshold to a fixed 1.8V threshold.
Once the output is in regulation (the first on-time is trig-
gered) and the PWRGD blanking time expires, the con-
troller tightens the OVP threshold, tracking the OVP
threshold by 300mV, subject to a minimum OVP thresh-
old of 0.8V. The controller also uses the fixed 1.8V OVP
threshold during soft-start and soft-shutdown.
When the OVP circuit detects an overvoltage fault, the
MAX17409 immediately forces DL high and pulls DH low.
This action turns on the synchronous-rectifier MOSFETs
with 100% duty and, in turn, rapidly discharges the output
filter capacitor and forces the output low. If the condition
that caused the overvoltage (such as a shorted high-side
MOSFET) persists, the battery fuse blows. Toggle SHDN
or cycle the V
CC power supply below 0.5V to clear the
fault latch and reactivate the controller.
OVP protection can be disabled through the no-fault
test mode (see the
No-Fault Test Mode section).
Output Undervoltage Protection (UVP)
The output UVP function is similar to foldback current
limiting, but employs a timer rather than a variable cur-
rent limit. If the MAX17409 output voltage is 400mV
below the target voltage, the controller activates the
shutdown sequence and sets the fault latch. Once the
controller ramps down to zero, it forces the DL high,
and pulls DH low. Toggle SHDN or cycle the V
CC
power
supply below 0.5V to clear the fault latch and reactivate
the controller.
UVP protection can be disabled through the no-fault
test mode (see the
No-Fault Test Mode section).
Thermal-Fault Protection
The MAX17409 features a thermal-fault protection cir-
cuit. When the junction temperature rises above
+160°C, an internal thermal sensor sets the fault latch
and forces the DL high and the DH low. Toggle SHDN
or cycle the V
CC
power supply below 0.5V to clear the
fault latch and reactivate the controller after the junction
temperature cools by 15°C. Thermal shutdown can be
disabled through the no-fault test mode (see the
No-
Fault Test Mode section).
No-Fault Test Mode
The latched fault protection features can complicate the
process of debugging prototype breadboards since
there are (at most) a few milliseconds in which to deter-
mine what went wrong. Therefore, a “no-fault” test
mode is provided to disable the fault protection—over-
voltage protection, undervoltage protection, and ther-
mal shutdown. Additionally, the test mode clears the
fault latch if it has been set. The no-fault test mode is
entered by forcing 11V to 13V on SHDN.
t
V
mV µs
TRAN SHDN
OUT
( )
. /
=
( )
1 56