Control interface, Rf12, Timing specification – Rainbow Electronics RF12 User Manual

Page 12

RF12

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Note 4:

Optimal antenna admittance/impedance:

RF12

Yantenna [S]

Zantenna [Ohm]

Lantenna [nH]

315 MHz

1.5E-3 -j5.14E-3

52 + j179

98.00

433 MHz

1.4E-3 -j7.1E-3

27 + j136

52.00

868 MHz

2E-3 -j1.5E-2

8.7 + j66

12.50

915 MHz

2.2E-3 -j1.55E-2

9 + j63

11.20

Note 5:

Adjustable in 8 steps.

Note 6:

With selective resonant antennas

Note 7:

During this period, commands are not accepted by the chip.

CONTROL INTERFACE

Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon

the rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal

is high, it initializes the serial interface. All commands consist of a command code, followed by a varying

number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits

having no influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default

values in all control and command registers.

The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the

nIRQ pin low - on the following events:

· The TX register is ready to receive the next byte (RGIT)

· The FIFO has received the preprogrammed amount of bits (FFIT)

· Power-on reset (POR)

· FIFO overflow (FFOV) / TX register under run (RGUR)

· Wake-up timer timeout (WKUP)

· Negative pulse on the interrupt input pin nINT (EXT)

· Supply voltage below the preprogrammed value is detected (LBD)

FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the

TX register is enabled. To identify the source of the IT, the status bits should be read out.

Timing Specification

Symbol Parameter

Minimum Value [ns]

Clock high time

Clock low time

Select setup time (nSEL falling edge to SCK rising edge) 10

Select hold time (SCK falling edge to nSEL rising edge)

SHI

Select high time

Data setup time (SDI transition to SCK rising edge)

Data hold time (SCK rising edge to SDI transition)

Data delay time