Rainbow Electronics U3742BM - Manual (Page 15)

15
U3742BM
4735A–RKE–11/03
Figure 14. Timing Diagram for Complete Successful Bit Check
Figure 15. Timing Diagram During Bit Check
Figure 16. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Bit check
Enable IC
DATA
1/2 Bit
Startup mode
(Number of checked bits: 3) Bit check ok
1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit
Receiving mode
Dem_out
Bit check mode
Bit check
Enable IC
Dem_out
Bit check counter
0 2 3 4 5 6 2 4 5 1 7 8 1 3 6 7 8 9 11121314 10
1/2 Bit
151617 18 1 2 3 4 5 6
(Lim_min = 14, Lim_max = 24)
7 8 9 1011121314 15 1 2 3 4
1/2 Bit 1/2 Bit
Bit check ok Bit check ok
T
Startup
T
XCLK
Bit check
Enable IC
Bit check counter
0 2 3 4 5 6 2 4 5 1 1 3 6 7 8 9 1112 10
1/2 Bit
Startup mode
0
(Lim_min = 14, Lim_max = 24)
Sleep mode
Bit check failed (CV_Lim < Lim_min)
Dem_out
Bit check mode