Toshiba TLP511E - Manual (Page 24)

6-3
6-2. Each IC Description
6-2-1. PLL IC CXA3106Q (QX028) for RGB Signals
A configuration of CXA3106Q is shown in Fig. 6-2-1.
The PLL IC of CXA3106Q is an IC with high perfor-
mance and low jitter, and can generate the clock signal
synchronized with the horizontal sync signal of max. 120
MHz.
The VCO, phase comparator, loop filter and frequency
dividing circuit are built in the IC, so the IC can generate
the clock signal by itself.
TTLIN
VCO
(TTL)
VCO
(PECL)
SYNC
(TTL)
SYNC
(PECL)
HOLD
(TTL)
TTLIN
TTLIN
PECLIN
PECLIN
POLARITY
PHASE
DETECTOR
CHARGE
PUMP
FINE
DELAY
VCO MUX
LATCH
COARSE
DELAY
POLARITY
TTLOUT
DSYNC
(TTL)
CLK
(TTL)
NCLK
(TTL)
CLK
(PECL)
CLK/2
(TTL)
NCLK/2
(TTL)
UNLOCK
VBB
CLK/2
(PECL)
DSYNC
(PECL)
TTLOUT
TTLOUT
TTLOUT
TTLOUT
PECLOUT
PECLOUT
PECL
2 bits 1 bit
1 bit
LOGIC
DIV
1 bit
2 bits 5 bits
12 bits
1 bit 2 bits 1 bit
RC 1 RC 2
1/16 20/16 CLK
ON/OFF
1 bit
ON/OFF
1 bit
ON/OFF
1 bit
ON/OFF
1/2
REST
1 bit
ON/OFF
1 bit
ON/OFF
1 bit
ON/OFF
READ OUT
TTLOUT
TTLOUT TTLIN
SYNTHESIZER
POWER SAVE
WHOLE CHIP
POWER WAVE
1 bit
1 bit
ON/OFF
1/256 1/4096
PROGRAMMABLE
COUNTER
DAC CONTROL REGISTER
1 REF
SENABLE SCLK SDATA SEROUT DIVOUT TLOAD CS
1 - 4 CLK
PECLOUT
UNLOCK
DETECT
Fig. 6-2-1