LSI 53C875A - Manual (Page 319)

Index IX-9
SEL 2-39
select 2-17
instruction 5-16
with ATN/ 5-20
with SATN/ on a start sequence (WATN) 4-22
selected (SEL) 4-74 , 4-77
selection or reselection time-out (STO) 4-75 , 4-79
selection response logic test (SLT) 4-87
selection time-out (SEL[3:0]) 4-84
semaphore (SEM) 4-49
serial EEPROM
interface 2-50
SERR/ 3-7
SERR/ enable (SE) 4-3
set instruction 5-15 , 5-17
set/clear
carry 5-20
SACK/ 5-21
shadow register test mode (SRTM) 4-59
SI_O/ status (I_O) 4-39
SID 2-51
SIDL
least significant byte full (ILF) 4-42
most significant byte full (ILF1) 4-46
SIEN0 2-39
SIEN1 2-39
signal process (SIGP) 4-49 , 4-54
signaled system error (SSE) 4-5
simple arbitration 4-20
single
address cycles 2-19
ended SCSI signals 6-6
step interrupt (SSI) 4-40 , 4-69
step mode (SSM) 4-71
SIP 2-38 , 2-41 , 2-42
SIST0 2-25 , 2-38 , 2-41 , 2-43
SIST1 2-38 , 2-41 , 2-43
slow ROM pin 3-15
SLPAR high byte enable (SLPHBEN) 4-27
SLPAR mode (SLPMD) 4-27
SMSG/ status (MSG) 4-39
SODL
least significant byte full (OLF) 4-42
most significant byte full (OLF1) 4-46
register 2-45 , 2-46 , 2-47
SODR
least significant byte full (ORF) 4-42
most significant byte full (ORF1) 4-46
software reset (SRST) 4-48
source I/O memory enable (SIOM) 4-67
special cycle command 2-4
SREQ 2-42
SREQ/ status (REQ) 4-39
SSEL/ status (SEL) 4-39
SSTAT0 2-25
SSTAT1 2-25
stacked interrupts 2-41
start
address 5-13 , 5-21
DMA operation (STD) 4-72
SCSI transfer (SST) 4-25
sequence (START) 4-21
static block move selector (SBMS) 4-102
STEST2 register 2-23
STOP command 2-9
stop signal 3-6
STOP/ signal 3-6
store 2-22
stress ratings 6-2
subsystem ID 2-51
subsystem ID (SID) 4-11
subsystem vendor ID 2-51
subsystem vendor ID (SVID) 4-10
SVID 2-51
SWIDE register 2-46 , 2-47
SXFER 2-36
SYNC_IRQD (SI) 4-51
synchronous
data transfer rates 2-34
operation 2-34
SCSI receive 2-31
SCSI send 2-30
synchronous clock conversion factor (SCF[2:0]) 4-29
system signals 3-4
T
table indirect 5-19
mode 5-18
table relative 5-20
target
mode 5-9 , 5-14
SATN/ active (M/A) 4-76
mode (TRG) 4-22
ready 3-6
timing 6-13
TCK 3-12
TDI 3-12
TDO 3-12
TEMP register 5-35
temporary (TEMP) 4-57
test interface signals 3-12
TEST_HSC/ 3-12
TEST_RST/ 3-12
third dword 5-35
timer test mode (TTM) 4-92
TMS 3-12
TolerANT 1-4 , 6-5
enable (TE) 4-91
technology 1-4
benefits 1-4
electrical characteristics 6-5
totem pole output 3-3
transfer
control 2-22
control instructions 5-25
and SCRIPTS instruction prefetching 2-22
counter 5-12 , 5-33
information 2-17
rate
synchronous 2-34
TRDY/ 2-9 , 3-6
TRST/ 3-12
U
Ultra SCSI 1-3
benefits 1-3
clock conversion factor bits 4-29
designing an Ultra SCSI system 2-20
enable (USE) 4-28