Index ix-7 – LSI 53C875A User Manual
Page 317
Index
IX-7
memory (Cont.)
read line command
read multiple
,
read multiple command
space
,
to memory
to memory moves
write
,
write and invalidate
write and invalidate command
write caching
write command
write enable
Min_Gnt (MG)
MOE/
move to/from SFBR cycles
multiple cache line transfers
MWE/
N
new capabilities (NC)
new features in the LSI53C875A
Next_Item_Ptr (NIP)
no connections
no download mode
no flush
store instruction only
not supported
O
opcode
,
fetch burst capability
operating conditions
operator
P
PAR
parallel ROM interface
parallel ROM support
parity
error
(PAR)
options
PCI
addressing
and external memory interface timing diagrams
bus commands and encoding types
bus commands and functions supported
cache line size register
cache mode
commands
configuration into enable (PCICIE)
configuration register read
configuration registers
configuration space
functional description
I/O space
interface signals
master transaction
master transfer
memory space
performance
target disconnect
target retry
PERR/
phase mismatch
handling in SCRIPTS
jump address 1 (PMJAD1)
jump address 2 (PMJAD2)
jump registers
physical dword address and data
PME
clock (PMEC)
enable (PEN)
status (PST)
support (PMES)
pointer SCRIPTS (PSCPT)
polling
power
and ground signals
management
state (PWS[1:0])
state D0
state D1
state D2
state D3
prefetch
enable (PFEN)
flush
flush (PFF)
SCRIPTS instructions
pull-ups, internal, conditions
R
RAM
see also SCRIPTS
RAM
read
line
function
modify-write cycles
multiple
multiple with read line enabled
write instructions
write system memory from SCRIPTS
read/write
instructions
,
system memory from SCRIPTS
received
master abort (from master) (RMA)
target abort (from master) (RTA)
register
address
address - A[6:0]
registers
relative
relative addressing mode
remaining byte count (RBC)
REQ/
request
reselect
during reselection
instruction
reselected (RSL)
,
reserved
,
,
,
,
,
,
,
,
,
,
,
,
,
,
command