LSI 53C875A - Manual (Page 108)

4-16 Registers
D2S D2_Support 10
The LSI53C875A sets this bit to indicate support for
power management state D2.
D1S D1_Support 9
The LSI53C875A sets this bit to indicate support for
power management state D1.
R Reserved [8:6]
DSI Device Specific Initialization 5
This bit is cleared to indicate that the LSI53C875A
requires no special initialization before the generic class
device driver is able to use it.
APS Auxiliary Power Source 4
Because the LSI53C875A does not provide a PME
signal, this bit is cleared, indicating that no auxiliary
power source is required to support the PME signal in the
D3cold power management state.
PMEC PME Clock 3
Bit 3 is cleared because the LSI53C875A does not
provide a PME pin.
VER[2:0] Version [2:0]
These three bits are set to 010 to indicate that the
LSI53C875A complies with Revision 1.1 of the PCI Power
Management Interface Specification.
Registers: 0x44–0x45
Power Management Control/Status (PMCSR)
Read/Write
PST PME Status 15
The LSI53C875A always returns a zero for this bit,
indicating that PME signal generation is not supported
from D3cold.
15 14 13 12 9 8 7 2 1 0
PST DSCL DSLT PEN R PWS[1:0]
0 0 0 0 0 0 0 0 x x x x x x 0 0