Intel 80L186EA - Manual (Page 7)

80C186EA 80C188EA 80L186EA 80L188EA
PCB
Function
Offset
20H Interrupt Vector
22H Specific EOI
24H Reserved
26H Reserved
28H Interrupt Mask
2AH Priority Mask
2C In-Service
2E Interrupt Request
30 Interrupt Status
32 TMR0 Interrupt Control
34 DMA0 Interrupt Control
36 DMA1 Interrupt Control
38 TMR1 Interrupt Control
3A TMR2 Interrupt Control
3C Reserved
3E Reserved
Figure 4 80C186EA Slave Mode Peripheral
Control Block Registers
DMA Control Unit
The 80C186EA DMA Contol Unit provides two inde-
pendent high-speed DMA channels Data transfers
can occur between memory and I O space in any
combination memory to memory memory to I O
I O to I O or I O to memory Data can be trans-
ferred either in bytes or words Transfers may pro-
ceed to or from either even or odd addresses but
even-aligned word transfers proceed at a faster rate
Each data transfer consumes two bus cycles (a mini-
mum of eight clocks) one cycle to fetch data and
the other to store data The chip-select ready logic
may be programmed to point to the memory or I O
space subject to DMA transfers in order to provide
hardware chip select lines DMA cycles run at higher
priority than general processor execution cycles
Chip-Select Unit
The 80C186EA Chip-Select Unit integrates logic
which provides up to 13 programmable chip-selects
to access both memories and peripherals In addi-
tion each chip-select can be programmed to auto-
matically terminate a bus cycle independent of the
condition of the SRDY and ARDY input pins The
chip-select lines are available for all memory and
I O bus cycles whether they are generated by the
CPU the DMA unit or the Refresh Control Unit
Refresh Control Unit
The Refresh Control Unit (RCU) automatically gen-
erates a periodic memory read bus cycle to keep
dynamic or pseudo-static memory refreshed A 9-bit
counter controls the number of clocks between re-
fresh requests
A 9-bit address generator is maintained by the RCU
with the address presented on the A9 1 address
lines during the refresh bus cycle Address bits
A19 13 are programmable to allow the refresh ad-
dress block to be located on any 8 Kbyte boundary
Power Management
The 80C186EA has three operational modes to con-
trol the power consumption of the device They are
Power Save Mode
Idle Mode and Powerdown
Mode
Power Save Mode divides the processor clock by a
programmable value to take advantage of the fact
that current is linearly proportional to frequency An
unmasked interrupt NMI or reset will cause the
80C186EA to exit Power Save Mode
Idle Mode freezes the clocks of the Execution Unit
and the Bus Interface Unit at a logic zero state while
all peripherals operate normally
Powerdown Mode freezes all internal clocks at a
logic zero level and disables the crystal oscillator All
internal registers hold their values provided V
CC
is
maintained Current consumption is reduced to tran-
sistor leakage only
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