HP XU800 - Manual (Page 67)

67
2 System Board
Host Bus
Cache Memory
The cache memory is sealed within a single Pentium III package that
contains the processor L1 and L2 cache.
The L1 cache memory has a total capacity of 32KB (16 KB data, 16 KB
instructions). The L2 cache memory has a capacity of i256 KB, and is
composed of four-way set-associative static RAM. Data is stored in lines of
32 bytes (256 bits). Thus two consecutive 128-bit transfers with the main
memory are involved in each transaction.
TagRam and Burst-pipelined Synchronous Static RAM (BSRAM) memories
and are implemented on die. Transfer rates between the processor’s core
and L2 cache are at full processor core clock frequency and scale with the
processor core frequency. Both the TagRam and BSRAM receive clocked
data directly from the processor’s core.
The amount of cache memory is set by Intel at the time of manufacture, and
cannot be changed.