Sundance SMT384 - Manual (Page 5)

Version 1.4 Page 5 of 47 SMT384 User Manual
AD9510 Register 12 – 0x42. ............................................................................... 40
AD9510 Register 13 – 0x43. ............................................................................... 40
AD9510 Register 14 – 0x44. ............................................................................... 41
AD9510 Register 15 – 0x45. ............................................................................... 41
AD9510 Register 16 – 0x46. ............................................................................... 41
AD9510 Register 17 – 0x47. ............................................................................... 41
AD9510 Register 18 – 0x48. ............................................................................... 42
AD9510 Register 19 – 0x49. ............................................................................... 42
PCB and Firmware Version Registers ................................................................ 42
FPGA Design.............................................................................................................. 43
Serial Interfaces ...................................................................................................... 43
Block of registers .................................................................................................... 44
Space available in FPGA ........................................................................................ 44
PCB Layout................................................................................................................. 44
Connectors ................................................................................................................. 46
Description .............................................................................................................. 46
Location on the board ............................................................................................. 47
Table of Figures
Figure 1 – Fan across PCI............................................................................................ 8
Figure 2 - Block Diagram............................................................................................ 11
Figure 3 - Main features. ............................................................................................ 14
Figure 4 - ADC Input Stage (AC coupling). ................................................................ 14
Figure 5 - ADC Input Stage (DC Coupling) ................................................................ 15
Figure 6 - Clock Structure........................................................................................... 15
Figure 7 - External Clock. ........................................................................................... 16
Figure 8 - Clock Architecture Main Characteristics. ................................................... 17
Figure 9 – Mezzanine module Connector Interface (SLB data and power connectors).
.................................................................................................................................... 18
Figure 10 – Mezzanine Module Interface Power Connector and Pinout. .................. 20
Figure 11 – Daughter Module Interface: Data Signals Connector and Pinout (Bank
A). ............................................................................................................................... 21