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Sundance SMT384 User Manual

Page 26

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Version 1.4

Page 26 of 47

SMT384 User Manual

Memory Map

The write packets must contain the address where the data must be written to and
the read packets must contain the address where the required data must be read.
The following figure shows the memory map for the writable and readable Control
Registers on the SMT384:

Address

Writable Registers

Readable Registers

0x00

Reset Register.

Reserved.

0x01

Test Register.

Reserved.

0x02

ADCA Register 0.

Read-back (FPGA Register) ADCA Register 0.

0x03

ADCA Register 1.

Read-back (FPGA Register) ADCA Register 1.

0x04

ADCA Register 2.

Read-back (FPGA Register) ADCA Register 2.

0x05

ADCB Register 0.

Read-back (FPGA Register) ADCB Register 0.

0x06

ADCB Register 1.

Read-back (FPGA Register) ADCB Register 1.

0x07

ADCB Register 2.

Read-back (FPGA Register) ADCB Register 2.

0x08

ADCC Register 0.

Read-back (FPGA Register) ADCC Register 0.

0x09

ADCC Register 1.

Read-back (FPGA Register) ADCC Register 1.

0x0A

ADCC Register 2.

Read-back (FPGA Register) ADCC Register 2.

0x0B

ADCD Register 0.

Read-back (FPGA Register) ADCD Register 3.

0x0C

ADCD Register 1.

Read-back (FPGA Register) ADCD Register 4.

0x0D

ADCD Register 2.

Read-back (FPGA Register) ADCD Register 5.

0x0E

0x0F

0x18

Reserved

Main Module Temperature

0x19

Reserved

Main Module FPGA Temperature

0x1A

Reserved

Mezzanine Module Temperature

0x1B

Reserved

Mezzanine Module Converter Temperature

0x1C

Misc Register (Trigger, Clock Selection, etc…).

Read- Misc Register.

0x1D

Update and Read-back command Register

Firmware Version and Status bits.

0x1E

Decimator Register

Decimator Register

0x30

AD9510 Register 0x0.

Read-back (FPGA Register) AD9510 Register 0.

0x31

AD9510 Register 0x1.

Read-back (FPGA Register) AD9510 Register 1.

0x32

AD9510 Register 0x2.

Read-back (FPGA Register) AD9510 Register 2.

0x33

AD9510 Register 0x3.

Read-back (FPGA Register) AD9510 Register 3.

0x34

AD9510 Register 0x4.

Read-back (FPGA Register) AD9510 Register 4.

0x35

AD9510 Register 0x5.

Read-back (FPGA Register) AD9510 Register 5.

0x36

AD9510 Register 0x6.

Read-back (FPGA Register) AD9510 Register 6.

0x37

AD9510 Register 0x7.

Read-back (FPGA Register) AD9510 Register 7.

0x38

AD9510 Register 0x8.

Read-back (FPGA Register) AD9510 Register 8.

0x39

AD9510 Register 0x9.

Read-back (FPGA Register) AD9510 Register 9.

0x3A

AD9510 Register 0xA.

Read-back (FPGA Register) AD9510 Register A.