Sundance SMT384 - Manual (Page 17)

Version 1.4 Page 17 of 47 SMT384 User Manual
Frequency range 10-125 MHz
External Sampling Clock Output
Output Voltage Level 0-2.4 Volts fixed amplitude.
Output Format LVTTL
External Trigger Inputs
Input Voltage Level 1.5-3.3 Volts peak-to-peak.
Format
DC-coupled and Single-ended (Termination
implemented at the connector). Differential
on option (3.3 V PECL).
Impedance 50-Ohm.
Frequency range 62.5 MHz maximum
Delay
External Ref. Input to Ext Ref. Out
External Clk Input to Ext Clk Out 11ns between J29 and J4
Figure 8 - Clock Architecture Main Characteristics.
Power Supply and Reset Structure
The SMT384 gets two power sources from the base module: 3.3 and 5 Volts. Linear
regulators are used to provide a clean and stable voltage supply to the analog
converters. The DC-coupling option uses also -12 Volts.
Green LEDs.
There are some LEDs on the Daughter Module. Three are dedicated for the power
supplies (3.3-Volt Channel A, B, C and D, as well as clock circuitry). Green LEDs
being ON meaning that the supply is under power.
Mezzanine module Interface
The daughter module interface is made up of two connectors (data and power). The
first one is a 0.5mm-pitch differential Samtec connector. This connector is for
transferring data such as ADC samples to the FPGA on the main module. The
second one is a 1mm-pitch Samtec header type connector. This connector is for
providing power to the daughter-card.
Sundance defines these two connectors as the Sundance LVDS Bus (SLB). It has
originally been made for data transfers using LVDS format but can also be used with
single-ended lines, which is the case for the SMT384. To know more about the SLB,
please refer to
the SLB specifications .
The figure underneath illustrates this configuration. The bottom view of the daughter
card is shown on the right. This view must the mirrored to understand how it connects
to the main module.