Sundance SMT384 User Manual
Page 31
Version 1.4
Page 31 of 47
SMT384 User Manual
ADCC Register 0 – 0x8
Setting
Bit 1
Description
0
0
PLL OFF – for sampling frequencies between 10 and 80 MHz
1
1
PLL ON – for sampling frequencies between 60 and 125 MHz
ADCC Register 1 – 0x9.
For more details, refer to ADS5500 datasheet.
ADCB Register 1 – 0x9
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Reserved TP1
TP0
Reserved
Default
‘000000’
‘0’ ‘0’ ‘0’
0
Reserved
Default
‘00000000’
ADCC Register 1 – 0x9
Setting
TP1
TP0
Description
0
0
0
Normal Mode of Operation
1
0
1
All outputs are zeroes
2
1
0
All outputs are ones
3
1
1
Continuous stream of ‘10’
ADCC Register 2 – 0xA.
For more details, refer to ADS5500 datasheet.
ADCC Register 2 – 0xA
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Reserved PDN
Reserved
Default
‘0000’ ‘0’
‘000’
0
Reserved
Default
‘00000000’
ADCC Register 2 – 0xA
Setting
PDN
Description
0
0
Normal Mode of Operation
1
1
Device in Power Down Mode