Sundance SMT384 - Manual (Page 14)

Version 1.4 Page 14 of 47 SMT384 User Manual
on option (3.3 V PECL).
Impedance 50-Ohm.
Frequency range 62.5 MHz maximum
ADCs Output
Output Data Width 14-Bits
Data Format
2’s Complement or offset binary
(Changeable via control register)
SFDR 82dBs maximum (manufacturer)
SNR 70dBs maximum (manufacturer)
Minimum Sampling Clock 10 MHz (ADC DLL off)
Maximum Sampling Frequency 125 MHz (ADC DLL on)
Figure 3 - Main features.
ADC Input Stage (standard SMT384).
Each ADC Analogue input is AC-coupled via and RF transformer. Both sides of the
transformers are balanced so the input is 50-Ohm single-ended.
Figure 4 - ADC Input Stage (AC coupling).
The SMT384 can also receive an DC-coupling input stage on request as shown
below :
It is based around a Texas Instrument amplifier (
THS4509 ), which gain is set to 6
dBs and is to match a 50-Ohm signal source.