Sundance SMT384 - Manual (Page 28)

Version 1.4 Page 28 of 47 SMT384 User Manual
1 1 Resets SHB (ADC ChA&B) interfaces.
Setting Bit 7 Description - SHB ADC C&D Reset
0 0 Normal Operation.
1 1 Resets SHB (ADC ChC&D) interfaces.
Note: The Reset bits don’t get cleared automatically, so a device can remain reset
while not used to reduce the global power consumption.
Test Register – 0x1.
Any 16-bit value written in this register can be read-back to check that the Comport
used works properly.
Test Register – 0x1
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0
1
ADCA Register 0 – 0x2.
For more details, refer to ADS5500 datasheet.
ADCA Register 0 – 0x2
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Reserved
Default ‘0000000’
0 Reserved PLL Reserved
Default ‘000000’ ‘0’ ‘0’
ADCA Register 0 – 0x2
Setting Bit 1 Description
0 0 PLL ON – for sampling frequencies between 60 and 125 MHz
1 1 PLL OFF – for sampling frequencies between 10 and 80 MHz
ADCA Register 1 – 0x3.
For more details, refer to ADS5500 datasheet.
ADCA Register 1 – 0x3
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Reserved TP1 TP0 Reserved
Default ‘000000’ ‘0’ ‘0’ ‘0’
0 Reserved
Default ‘00000000’
ADCA Register 1 – 0x3