Control register settings – Sundance SMT384 User Manual

Page 25

Version 1.4

Page 25 of 47

SMT384 User Manual

Control Register Settings

The Control Registers control the complete functionality of the SMT384. They are
setup via the Comport0 or 3 (the default firmware implements Comport3 only). The
settings of the ADCs, triggers, clocks and the configuration of the SHB interfaces and
the internal FPGA data path settings can be configured via the Control Registers.

Control Packet Structure

The data passed on to the SMT384 over the Comports must conform to a certain
packet structure. Only valid packets will be accepted and only after acceptance of a
packet will the appropriate settings be implemented. Each packet will start with a
certain sequence indicating the start of the packet (0xFF). The address to write the
data payload into will follow next. After the address the data will follow. This structure
is illustrated in the following figure:

Byte Content

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’

Address 7

Address 6

Address 5

Address 4

Address 3

Address 2

Address 1

Address 0

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

Figure 14 – Setup Packet Structure.

Reading and Writing Registers

Control packets are sent to the SMT384 over Comport 0 or 3. This is a bi-directional
interface. The format of a ‘Read Packet’ is the same as that of a write packet.

Host

Fixed Sequence

SMT350

ComPort 0 or 3

Byte 0

Read/Write Address

Byte 1

Read/Write Data

Byte 3

Read/Write Data

Byte 4

1) Write Packet

Figure 15 – Control Register Read Sequence.