Sundance SMT384 - Manual (Page 12)

Version 1.4 Page 12 of 47 SMT384 User Manual
digitized. ADCs get their own sampling clock, which can be either on-board
generated or from an external reference or an external clock, common to all ADCs
(MMCX connector). Digital samples travel to the FPGA on the base module via the
inter-module connector (
SLB – Sundance LVDS Bus, used in this case as ‘single-
ended’).
Clock generator and distribution: All samplings clocks are generated by the same
chip. It allows having them all synchronized to a single reference clock. The on-board
clock uses the VCXO locked on an on-board 10MHz reference. The reference also
can be external, in that case the VCXO is still used. In the case of an external clock,
the VCXO is no longer used as the AD9510 then acts as a clock multiplexer. In all
cases, all sampling clocks are synchronized to the same clock source.
Multi-module Synchronization: SMT384s can be cascaded and still be synchronized
as either the external reference or the external clock can be passed the next module
in the chain. The external reference goes through a 0-delay buffer and is then output.
Please note that symchronisation is in frequency and not in phase.
Inter-module Connector: it is made of a power (33 pins) and data connectors (120
pins). It is called Sundance LVDS Bus. Please refer to
the SLB specifications for
more details. In the case of the SMT384, the SLB is used as ‘single-ended’.
A global reset signal is mapped to the FPGA from the bottom TIM connector.
External Clock signals, used to generate Sampling clocks. There is one external
clock, common to all four ADCs. When used, the AD9510 is used as a clock
multiplexer. Also available, an external reference clock that can be passed to an
other SMT384 (cascaded modules) module with ‘0-delay’.
External Trigger: passed directly to the base module. There are two, one for each
pair of ADCs (Channel A & B and Channel C & D).
Temperature Sensor: available for constant monitoring.