Measurement Computing CIO-DAS16 - Manual (Page 27)

4.7 DMA, INTERRUPT & TRIGGER CONTROL
BASE ADDRESS + 9
TS0 TS1 DMA Don’t Care IR1 IR2 IR4 INTE
0 1 2 3 4 5 6 7
A read and write register.
READ OR WRITE:
INTE = 1, Interrupts are enabled. An interrupt generated will be placed on the PC bus interrupt level selected by IR4,
IR2, and IR1. When INTE = 0, interrupts are disabled.
IR4, IR2, and IR1 are bits in a binary number between 0 and 7 which map interrupts onto the PC bus interrupt levels 2 to
7. Interrupts 0 and 1 can not be asserted by the CIO-DAS16.
When DMA = 1, DMA transfers are enabled. When DMA = 0, DMA transfers are disabled. Note that a DMA request
can be asserted only on the DMA request level selected by the DMA switch on the board. Before this bit is set to 1, the
PC's 8237 (or appropriate) DMA controller chip must be set up.
TS1 & TS0 control the source of the A/D start conversion trigger according to Table 4-3 below.
Table 4-3. Start Conversion Trigger Source - Control Bit Coding
Start on Pacer Clock Pulse (CTR 2 OUT, no external access) 1 1
Start on rising TRIGGER (Digital input 0, Pin 25) 0 1
Software triggered A/D only X 0
Action TS0 TS1
4.8 PACER CLOCK CONTROL REGISTER
BASE ADDRESS +10
TRIG0 CTR0 X X X X X X
0 1 2 3 4 5 6 7
Write only
When CTR0 = 1, an on-board 100 KHz clock signal is ANDed with the COUNTER 0 CLOCK INPUT (pin 21). A high
on pin 21 will allow pulses from the on-board source into the 8254 Counter 0 input.
When CTR0 = 0, the input to 82C54 Counter 0 is entirely dependent on pulses at pin 21, COUNTER 0 CLOCK INPUT.
TRIG0 = 1. The TRIGGER input at pin 25 is ANDed with TRIG0 which controls gating of the on-board pacer clock
(82C54). When TRIG0 = 1, the on-board pacer clock can be gated off (disabled) by pulling pin 25 low. The input at pin
25 is pulled up and will always be high unless pulled low externally.
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