1 mdio – Artesyn COMX-P40x0 ENP2 Installation and Use (January 2015) User Manual
Page 82
Functional Description
COMX-P40x0 ENP2 Installation and Use (6806800R95C)
82
4.12.1 MDIO
There are two groups of MDIO buses in the P40x0 CPU. The first group called EMI1 complies
with IEEE 802.3 Clause 22 and is used for management of the 1Gb Ethernet connection on
modules with that option, and management of SerDes interfaces configured as SGMII. EMI1
has two pins: EMI1_MDC and EMI1_MDIO. All dTSEC interfaces in the P40x0 CPU share the
same management hardware. External PHY access for all ports is available through the dTSEC1
registers of FM1. EMI1 is based on +2.5 V signaling levels.
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