Artesyn COMX-P40x0 ENP2 Installation and Use (January 2015) - Manual (Page 69)

Functional Description
COMX-P40x0 ENP2 Installation and Use (6806800R95C) 69
Features of e500mc
 36-bit physical addressing
 512-entry 4 KB pages
 3 Integer units (2 simple, 1 complex)
 1.2 GHz at 1.0V
 64 Byte cache line size
 L1 caches
 User, Supervisor, and Hypervisor instruction level privileges
 APU, classic double precision floating point unit
 128 KB private L2 cache running at the same frequency of CPU
 2 MB of shared L3 CoreNet platform cache (CPC)
4.4 Integrated Memory Controller
The P4080/P4040 processor integrates two DDR controllers that support DDR2 and DDR3
SDRAM. It can support a maximum of 64 GB of main memory. ENP2 modules are limited to 8
GB, using 4 Gb devices.The ECC capability detects all double-bit errors, detects all multi-bit
errors within a nibble, and corrects all single-bit errors. The DDR controller is capable of self-
refresh mode and an initialization bypass during system power-on after an abnormal shutdown
for use by designers in preventing re-initialization.
4.5 Local Bus
The 16-bit wide local bus is connected to a 2 Gb or 256 MB NOR Flash and an 8 Gb or 1 GB NAND
FLASH. The NOR FLASH is used to store the RCW data (active and alternates), FMan microcode,
DTB, U-Boot, demo Linux kernel and associated basic ramdisk. By default, the NAND FLASH is
used to store an alternate Linux file system. The local bus is also extended to the COM Express
connectors. There are six chip select signals supported - CS0, CS1 and CS3-6. CS0 is reserved
for the boot device and defaults to the NOR FLASH. CS1 defaults to the NAND FLASH. CS0 and
CS1 can be swapped between the NOR and NAND FLASH by driving the COM Express
connector pin A30 high (+3.3 V). CS3-6 are extended to the COM Express connector and are
available for use.