Artesyn COMX-P4080 Installation and Use (August 2014) - Manual (Page 65)

Functional Description
COMX-P4080 COM Express Module Installation and Use (6806800L20C) 65
4.8 LAN
The COMX-P4080 has one Gigabit port with an LED that shows the controlling signals. It is
routed to the COM-E connectors. The interface between MAC and PHY BCM5482 is the first
group of the RGMII bus and is multiplexed with ULPI bus. The RCW should then be properly set
to select the RGMII protocol.
There are two ports included in the GE PHY BCM5482, the first of which is the only one available
in the COMX-P4080 platform. Both ports are available in the P30 and P50 platforms.
The COMX-P4080 has two groups of MDIO buses. The first group is called EMI1 and compiles
with IEEE 802.3 Clause 22 standard. It has two pins, EMI1_MDC and EMI1_MDIO and is
available externally only on dTSEC0@FMan1. This group is used for the communication
between the MAC and PHY. It also manages SGMII PHY.
The second group is called EMI2 and it complies with IEEE 802.3ae Clause 45. EMI2 has two
pins: EMI2_MDC and EMI2_MDIO and is available externally only on 10GEC of FMan1. EMI2 is
used for the communication between 10GEC and PHY.
The ports in the BCM5482 has two LED controlling signals: LAN1_LINK_ACTIVITY_N and
LAN_LINKSPEED_N. The COM-E connectors have four LED controlling signals: link, activity,
link_100 and link_1000. The link and activity signals are attached to the LAN1_LINK_ACTIVITY
of the BCM5482. Link_1000 is connected to LAN1_LINKSPEED_N and link_100 is left
disconnected.
11 PEX1 x4 (2.5 Gbps) SRIO1 x4 (2.5 Gbps) XAUI (3.125 Gbps) OFF OFF
12 PEX1 x4 (5 Gbps) SRIO1 x4 (2.5 Gbps) XAUI (3.125 Gbps) OFF OFF
Table 4-7 SerDes Options When Routed to COM-E Connectors (continued) (continued)
Option
Bank 1
SerDes 0 ~ 3
(Slot J6) Bank 1
SerDes 4 ~ 7
(Slot J14) Bank 2
SerDes 10 ~ 13
(Slot J10)
S1.2 (Bank 1
RefClock)
S1.3/S1.4
(Bank 2/3
RefClock)