Artesyn COMX-P4080 Installation and Use (August 2014) - Manual (Page 63)

Functional Description
COMX-P4080 COM Express Module Installation and Use (6806800L20C) 63
As with Table "RCW Source Location" on page 60 , the "X" on the table indicates the "ON" or "OFF"
state of the corresponding bits of the S2 switch.
4.7 SerDes
The COMX-P4080 has three Serializer/Deserializer (SerDes) banks, including a total of 18 lanes.
Twelve of these are routed to the COM-E connectors, defined as SERDES0 - SERDES7 (SERDES0-
7 of bank 1), and SERDES16 - SERDES19 (SERDES10-13 of bank 2). SERDES8-SERDES9 of bank
1 are used for Aurora debugger . The four lanes of bank 3 are not used in COMX-P4080 and are
reserved for the P30 and P50 series SATA interfaces.
The protocol running at each lanes that are routed to COM-E connectors are configured by the
RCW. The following table shows the available options.
The U-Boot provides commands to change the configurations, allowing the user to select any
of the twelve options available. In addition, the frequency of the reference clock for each bank
should be properly configured based on the
Clock Distribution .
ON,OFF,ON,ON,ON Two (x4, x4) SRIO @ 2.5G, 100MHz ref clk, all agent mode;
All cores in boot hold-off;
Dual 4-pin UART enabled;
Platform ratio of 6:1; Core PLL ratio of 10:1
ON,OFF,OFF,X,X Reserved
Table 4-6 RCW Hard-Coded Configuration Options (continued)
S2.1-S2.5 RCW hard-code configuration options