Altera Transceiver Signal Integrity Development Kit, Stratix V GX Edition - Manual (Page 54)

A–2 Appendix A: Board Revision History
Engineering Silicon Version Differences
Transceiver Signal Integrity Development Kit July 2012 Altera Corporation
Stratix V GX Edition Reference Manual
Engineering Silicon Version Differences
The engineering silicon version of the Stratix V GX transceiver signal integrity
development board is the initial release of the board. This section describes the
differences between the engineering silicon and production silicon versions of the
board.
Power Supply
Table A–2 lists information for the targeted power rails whose voltage values on the
engineering silicon board differ from the production silicon board. Table 2–40 on
page 2–39 shows the production silicon voltage values.
Table A–2. Power Requirements (Engineering Silicon)
Device Voltage Name Voltage (V) Note
FPGA
S5GX_VCC 0.85
VCC
VCCHIP
VCCHSSI
2p5V 2.5
VCCIO
VCCPD
VCCREF
VCCPGM
VCCBAT
VCC_CLKIN
2p5V_FLTR 2.5
Ferrite fitered from 2p5V,
VCCA_PLL, and VCCAUX
1p5V 1.5
VCCPT
VCCH_GXB
VCCD_FPLL
VCCBAT 1.5 BT1 socket
VCCR_GTB (28G channels) 0.85 or 1.0 LDO
VCCT_GTB (28G channels) 0.85 or 1.0 LDO
VCCL_GTB (28G channels) 0.85 or 1.0 LDO
VCCRT_GXB 0.85 or 1.0 Low noise switcher
VCCA_GXB 2.5 or 3 Low noise switcher
VCCH_GXB 1.5 Tied to 1p5V (low noise switcher)
MAX V (for FPP configuration) 2p5V 2.5 —
Flash
2p5V 2.5 Core
XFP_1p8V 1.8 I/O
MAX II (for USB-Blaster) 2p5V 3.3 Core or I/O
EEPROM USBVCC 5.0 —
USB PHY
USBVCC 5.0 Core
2p5V_USB 2.5 I/O
Power monitor 5V 5.0 —