Altera Transceiver Signal Integrity Development Kit, Stratix V GX Edition - Manual (Page 41)

Chapter 2: Board Components 2–33
Components and Interfaces
July 2012 Altera Corporation Transceiver Signal Integrity Development Kit
Stratix V GX Edition Reference Manual
Components and Interfaces
This section describes the development board's communication ports and interface
cards relative to the Stratix V GX device. The development board supports the
following components and interfaces:
■ 10/100/1000 Ethernet
■ Transceiver interfaces
■ XFP interface
■ SFP+ interface
10/100/1000 Ethernet
The development board supports a 10/100/1000 BASE-T Ethernet connection using a
Marvell 88E1111 PHY device and the Altera Triple-Speed Ethernet MegaCore MAC
function. The device is an auto-negotiating Ethernet PHY with an SGMII interface to
the FPGA. The Stratix V GX device can communicate with the LVDS interfaces at up
to 1.25 Gbps. The MAC function must be provided in the FPGA for typical
networking applications. The Marvell 88E1111 PHY uses 2.5-V and 1.2-V power rails
and requires a 25-MHz reference clock driven from a dedicated oscillator. It interfaces
to an RJ-45 with internal magnetics that can be used for driving copper lines with
Ethernet traffic.
Figure 2–9 shows the SGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
Table 2–32 lists the Ethernet PHY interface pin assignments.
Figure 2–9. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
MAC
88E1111
Device
Transformer RJ45
SGMII Interface
S_IN ±
S_OUT ±
CAT 5 UTP:
- 10BASE-T
- 100BASE-TX
- 1000BASE-T
Table 2–32. Ethernet PHY Pin Assignments, Signal Names and Functions
Board
Reference
(U22)
Schematic Signal Name I/O Standard
Stratix V GX Device
Pin Number
Description
23 ENET_INTN 2.5-V AL14 Management bus Interrupt
70 ENET_LED_DUPLEX 2.5-V — Duplex LED
76 ENET_LED_LINK10 2.5-V — 10-Mb link LED
74 ENET_LED_LINK100 2.5-V — 100-Mb link LED