Altera Transceiver Signal Integrity Development Kit, Stratix V GX Edition - Manual (Page 28)

2–20 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Transceiver Signal Integrity Development Kit July 2012 Altera Corporation
Stratix V GX Edition Reference Manual
Table 2–11 lists the DIP switch component reference and manufacturing information.
Program Select Jumper
The program select jumper, PGMSEL, (J28) is an input to the MAX II CPLD System
Controller. After a power-on or reset configuration, the MAX II CPLD System
Controller configures the FPGA to either factory or user image. For information on the
jumper settings, refer to
“FPGA Programming from Flash Memory” on page 2–15 .
Reset Push Button
The reset push button, RESETn, is an input to the MAX II CPLD System Controller. This
push button is the default logic reset for the CPLD logic.
Table 2–12 lists the MAX II reset push button component reference and manufacturing
information.
CPU Reset Push Button
The CPU reset push button, CPURSTn, (S6) is connected to a regular I/O pin of the
FPGA and serves as a reset for the NIOS II when you load the application.
Table 2–13 lists the CPU reset configuration push button component reference and
manufacturing information.
Table 2–11. FPP Configuration/MAX II Bypass DIP Switch Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturer
Part Number
Manufacturer Website
S7 Six-Position slide DIP switch Grayhill 97C06RT www.grayhill.com
Table 2–12. MAX II Reset Push Button Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturer
Part Number
Manufacturer
Website
S5 Push Button Panasonic Corporation EVQPAC07K www.panasonic.com
Table 2–13. CPU Reset Configuration Push Button Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturer
Part Number
Manufacturer
Website
S6 Push Button Panasonic Corporation EVQPAC07K www.panasonic.com