Altera Stratix IV GX FPGA Development Board - Manual (Page 55)

Chapter 2: Board Components 2–47
Components and Interfaces
November 2010 Altera Corporation Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
The LMH0344 cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD, and
3.0 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling
the device, as well as a carrier detect or auto-mute signal interface.
Table 2–44 shows the cable equalizer lengths.
Table 2–45 summarizes the SDI video input interface pin assignments. The signal
names and directions are relative to the Stratix IV GX FPGA.
Figure 2–14 shows the SDI cable equalizer.
Table 2–44. SDI Cable Equalizer Lengths
Data Rate (Mbps) Cable Type Maximum Cable Length (m)
270
Belden 1694A
400
1485 140
2970 120
Table 2–45. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions
Board
Reference
Description
Schematic
Signal Name
I/O Standard
MAX II CPLD EPM2210
System Controller
Pin Number
Stratix IV GX Device
Pin Number
U2.11 SDI video input P SDI_RX_P
1.4-V PCML
— L2
U2.10 SDI video input N SDI_RX_N — L1
U2.7 Bypass enable SDI_RX_BYPASS
2.5-V
T4 —
U2.14 Device enable SDI_RX_EN M6
—
(Automatically driven
by carrier detect)
Figure 2–14. SDI Cable Equalizer
BYPASS
MUTE
REF
1.0 μF
75 Ω
37.4 Ω
1.0 μF
1.0 μF
CD
SDI
SDI
SDO
SDO
CD
MUTE
MUTE
REF
BYPASS
AEC+ AEC–
75 Ω
MUTE
Coaxial Cable
LMH0344 3G SDI
Adaptive Cable
Equalizer
To FPGA
3.9 nH