Clock circuitry, Clock circuitry –21 – Altera Stratix IV GX FPGA Development Board User Manual
Page 29
Chapter 2: Board Components
2–21
Clock Circuitry
November 2010
Altera Corporation
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual
lists the rotary switch component reference and manufacturing
information.
Clock Circuitry
This section describes the board's clock inputs and outputs.
D
S4VCCIO_B3B4
1.5
VCCIO_B3
Bank 3 I/O power (DDR3BOT)
VCCIO_B4
Bank 4 I/O power (DDR3BOT)
E
S4VCC_GXB
1.1
VCCR
XCVR analog receive
VCCT
XCVR analog transmit
VCCL_GXB
XCVR clock distribution
F
12 V
12
—
All 12 V power
Table 2–18. Power Rail Measurements Based on the Rotary Switch Position (Part 2 of 2)
Switch
Schematic Signal Name
Voltage (V)
Device Pin
Description
Table 2–19. Rotary Switch Component Reference and Manufacturing Information
Board Reference
Description
Manufacturer
Manufacturer
Part Number
Manufacturer
Website
SW2
16-position rotary
switch
Grayhill Corporation
94HCB16WT
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)