Altera Stratix IV GX FPGA Development Board - Manual (Page 42)

2–34 Chapter 2: Board Components
Components and Interfaces
Stratix IV GX FPGA Development Board, 530 Edition Reference Manual November 2010 Altera Corporation
Figure 2–10 shows the SGMII interface between the FPGA (MAC) and Marvell
88E1111 PHY.
Table 2–35 lists the Ethernet PHY interface pin assignments.
Table 2–36 lists the Ethernet PHY interface component reference and manufacturing
information.
Figure 2–10. SGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
MAC 88E1111
Device
Transformer RJ45
SGMII Interface
S_IN ±
S_OUT ±
CAT 5 UTP:
- 10BASE-T
- 100BASE-TX
- 1000BASE-T
Table 2–35. Ethernet PHY Pin Assignments, Signal Names and Functions
Board Reference Description Schematic Signal
Name
I/O Standard
Stratix IV GX
Device
Pin Number
U21.82 SGMII TX data ENET_TX_P
LVDS
L29
U21.81 SGMII TX data ENET_TX_N K29
U21.77 SGMII RX data ENET_RX_P AC31
U21.75 SGMII RX data ENET_RX_N AC32
U21.25 Management bus control ENET_MDC
2.5-V
AH34
U21.24 Management bus data ENET_MDIO M33
U21.23 Management bus interrupt ENET_INTn R30
U21.28 Device reset ENET_RESETn V31
Table 2–36. Ethernet PHY Component Reference and Manufacturing Information
Board Reference Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U21 Ethernet PHY BASE-T device
Marvel
Semiconductor
88E1111-B2-CAAIC000 www.marvell.com